Shared Cache Lab

​With over 16 years in Design Verification and a decade focused specifically on shared cache micro-architecture, I’ve had the privilege of taking complex L2 and L3 designs from blank-page concepts to successful tape-outs at Samsung and Google.

​My journey has spanned the evolution of interconnect protocols—from AXI and AHB to the complexities of AMBA CHI. Today, I lead a team of nine engineers at Google, where we are responsible for verifying the shared cache subsystems powering next-generation CPUs. Our current focus is on the intersection of traditional coherence and the massive throughput demands of AI/ML workloads and Scalable Matrix Extension (SME) architectures.

​Shared Cache Lab is where I document the lessons learned from verifying silicon at scale, mastering the architecture between the cores, and solving the unique challenges of modern, high-performance memory hierarchies.