Welcome: Why Shared Cache Matters
After 16 years in design verification—from the early days of AXI to leading next-gen AI-centric cache units at Google—I’ve realized that the shared cache is often the most misunderstood part of the chip. It’s the “negotiator” between the cores, and when it fails, the whole system collapses.
I’m starting Shared Cache Lab to pull back the curtain on this niche.
To the Students: The Bridge to Silicon
If you’re just starting out, the jump from textbook MESI protocols to a 10-million-gate L2 unit can feel like a cliff. You won’t find the “real” challenges in a classroom. Here, I’ll help you navigate the transition from academic logic to the industry-standard protocols like AMBA CHI that actually power the world’s most advanced CPUs. We’ll focus on how to think like a verification engineer: don’t just ask “does it work?”—ask “how does it break?”
To the Professionals: Solving for Complexity
For my peers, this blog is a space for the “hard stuff.” We’ll dive into the deep end:
- Verifying Scalable Matrix Extension (SME) workloads.
- Managing cache coherence for massive AI/ML data flows.
- The architectural trade-offs between snoop filter accuracy and silicon area.
We’re at a point where traditional verification isn’t enough; we have to influence the micro-architecture itself to make it verifiable.
I’ve seen plenty of tape-outs and plenty of bugs. My goal is to share the patterns I’ve seen so we can all build better, more reliable silicon. Let’s get to work.
Shared Cache Lab 